there are so many cores

Just another site

Diagram the design a little

After this last pause in development, I found myself asking, “How does this work?” The design has become quite complex. Any time away and it fades from memory.

So I am spending time to create design artifacts.

Flow from user application to the scheduler:

Interaction between scheduler threads:

wait(ptid, trace)        _traceMap        _boss        _work

   ------------------signal-----------------> WAKE UP
                                             --broadcast-> WAKE UP
                                              SLEEP        COLLATE
                                                           REMOVE FLAG

Flow from the scheduler to devices:

The complex stuff is under the translator inside the jit/ module. I want to spend a little time diagramming the JIT before integrating GATLAS.


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